1. Field of the Invention
The present invention relates to a display device capable of easily displaying gray scale images using an EL element or the like, and an electronic apparatus having the display device.
2. Description of the Related Art
In recent years, a display device using a light emitting element typified by an electro luminescence element (hereinafter referred to as an EL element) has been actively developed. The EL element includes the one utilizing luminescence generated from an excited singlet state and the one utilizing luminescence generated from an excited triplet state. The EL element generally adopts a stacked structure where a light emitting layer is sandwiched between a pair of electrodes (anode and cathode). For example, there is a stacked structure of a hole transporting layer, a light emitting layer, and an electron transporting layer. Also known is a stacked structure where a hole injection layer, a hole transporting layer, a light emitting layer, and an electron transporting layer are stacked, or a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injection layer are stacked in this order on an anode (see Patent Document 1, for example).
[Patent Document 1] Japanese Patent Laid-Open No. 2001-343933
As an LED driving device capable of adjusting the luminance of a light emitting element such as an LED to display gray scale images, suggested was a display device capable of varying the luminance of an LED display array by changing an LED emission time of the LED display array in one scanning period, namely by changing duty ratio (see Patent Document 2, for example).
[Patent Document 2] Japanese Patent Laid-Open No. H5-341728
In the aforementioned conventional display device, the duty ratio of an LED varies in accordance with external luminance data, therefore, gray scale images are displayed by controlling the external luminance data and light emission time rate is adjusted by varying the duty ratio of a light emitting data pulse. In the case of such an LED display device, pulse time interval of light emission data is equal to each other in all fields. Thus, the number of gray scale levels is required to be equal to that of fields and the number of fields is required to be increased to increase the number of gray scale levels, resulting in limited number of gray scale levels that can be displayed.
On the other hand, as a display device capable of multi-gray scale displaying using the aforementioned EL element, there is a known display device adopting a digital gray scale method and a time gray scale method (Patent Document 1).
The time gray scale method is a method of displaying gray scale images by controlling an EL element emission time, which will be described with reference to FIGS. 23 to 26. As shown in FIGS. 23 and 24, an EL display device has a pixel portion 101 including a pixel 105 that is arranged in matrix using a TFT (thin film transistor) on a substrate, and a source signal line driver circuit 102, a writing gate signal line driver circuit 103, and an erasing gate signal line driver circuit 104 that are disposed at the periphery of the pixel portion 101. The source signal line driver circuit 102 has a shift register 102a, a latch 102b, and a latch 102c. 
The pixel portion 101 has source signal lines (S1 to Sx) connected to the latch 102c of the source signal line driver circuit 102, power supply lines (V1 to Vx), writing gate signal lines (Ga1 to Gay) connected to the writing gate signal line driver circuit 103, and erasing gate signal lines (Ge1 to Gey) connected to the erasing gate signal line driver circuit 104. Each of the signal lines is connected to the corresponding pixel 105 arranged in matrix. Note that reference numeral 106 denotes a time division gradation data signal generation circuit.
The pixel 105 has, as shown in FIG. 25, a switching TFT 107, an EL driving TFT 108 connected to an EL element 110, an erasing TFT 109, and a capacitor 112. A gate electrode of the switching TFT 107 is connected to a writing gate signal line Ga, one of a source region and a drain region thereof is connected to a source signal line S, and the other is connected to a gate electrode of the EL driving TFT 108, the capacitor 112 in each pixel, and a source region or a drain region of the erasing TFT 109. The capacitor 112 is provided in order to hold a gate voltage of the EL driving TFT 108 when the switching TFT 107 is off (non-selected state).
One of a source region and a drain region of the EL driving TFT 108 is connected to a power supply line V and the other is connected to the EL element 110. The power supply line V is connected to the capacitor 112. The source region or the drain region of the erasing TFT 109, which is not connected to the switching TFT 107, is connected to the power supply line V, and a gate electrode thereof is connected to a gate signal line Ge.
The operation and gray scale display of the EL display device are hereinafter described with reference to FIG. 26. When a writing selection signal is inputted from the writing gate signal line driver circuit 103, the switching TFTs 107 in all the pixels connected to the writing gate signal line Ga1 of the first row are turned on. At the same time, the first bit digital data “0” or “1” of a video signal that is converted into a digital signal is inputted to the source signal lines S1 to Sx from the latch 102c. This digital data is inputted to the gate electrode of the EL driving TFT 108 through the switching TFT 107. When the digital data is “1”, the EL driving TFT 108 is turned on and the EL element 110 emits light. Meanwhile, when the digital data is “0”, the EL driving TFT 108 is turned off and the EL element 110 emits no light.
As set forth above, when the digital data is inputted to the pixels of the first row, the EL element emits light or no light, thereby the pixels of the first row display images. Here, a display period of a pixel is denoted by Tr, a display period of a pixel to which the first bit digital data is inputted is denoted by Tr1, and display periods by the digital data of the subsequent bits are sequentially denoted by Tr2, Tr3 . . . as shown in FIG. 26.
When the input of the writing selection signal to the writing gate signal line Ga1 is completed, a writing selection signal is similarly inputted to the writing gate signal line Ga2. Then, the switching TFTs 107 in all the pixels connected to the writing gate signal line Ga2 are turned on, and the first bit digital data is inputted to the pixels of the second row from the source signal lines S1 to Sx. A writing period Ta1 is a period where writing selection signals are sequentially inputted to all the writing gate signal lines (Ga1 to Gay) to select all the writing gate signal lines and the first bit digital data is inputted to the pixels of all the rows.
On the other hand, before the first bit digital data is inputted to the pixels of all the rows, that is, before the completion of the writing period Ta1, an erasing selection signal is inputted to the erasing gate signal line Ge1 from the erasing gate signal line driver circuit 104 at the same time as the input of the first bit digital data to the pixels. Then, the erasing TFTs 109 in all the pixels (pixels of the first row) connected to the erasing gate signal line Ge1 are turned on, and power supply potentials of the power supply lines (V1 to Vx) are supplied to the gate electrodes of the EL driving TFTs 108, thereby the EL driving TFTs 108 are turned off. Accordingly, the power supply potentials are not supplied to pixel electrodes of the EL elements 110, and all the EL elements 110 in the pixels of the first row emit no light, thus the pixels of the first row display no image. A non-display period where the pixels display no image after the data is erased is denoted by Td as shown in the drawing, and a non-display period of the first row is denoted by Td1.
Data writing and erasing are performed in the subsequent row similarly to the first row, thereby the first bit digital data of the pixels of all the rows is erased. An erasing period where the first bit digital data of the pixels of all the rows is erased is denoted by Te1 as shown in the drawing. An erasing period of the second bit digital data is denoted by Te2.
The operations of displaying, erasing, and non-displaying are thus repeated until the n-th bit digital data is inputted to the pixels, and a displaying period Tr and a non-displaying period Td alternately appear. When all the display periods (Tr1 to Trn) are completed, one image, namely an image of one frame can be displayed.
In the EL display device performing the aforementioned operations, the length of the display period Tr is set such that Tr1:Tr2: . . . Trn=20:21: . . . 2(n−1) to display gray scale images. By combining the display periods, a desired level gray scale display selected from 2n-level gray scale can be performed. The gray scale level of an image displayed in a pixel in one frame is determined by the sum of display periods where an EL element emits light in the frame. For example, in the case of n=8 (256-level gray scale), on the assumption that luminance when a pixel emits light in all the display periods is 100%, a luminance of 1% is achieved when the pixel emits light in Tr1 and Tr2, while a luminance of 60% is achieved when the pixel emits light in Tr3, Tr5, and Tr8.
In other words, on the assumption that display time/(display time+non-display time)=display time rate and display time rate at the maximum gray scale level is the maximum value of the display time rate in one frame period, gray scale images are displayed with the maximum value of the display time rate fixed as shown in FIG. 9. When the maximum value of the display time rate is fixed, the power consumption of a display means (EL display panel) increases with the increase in gray scale levels as described below. FIG. 14B is an experimental result showing that the number of display gray scale levels decreases if luminance is varied by reducing gray scale level. In FIG. 14B, bit corresponds to the number of gray scale levels whereas duty corresponds to the display time rate. If a pixel constituting a display means includes an EL element that is a light emitting element, the display time and the non-display time are equivalent to a light emission time and a non-light emission time, and thus the display time rate in FIG. 9 is a light emission time rate.